1. Field of the Invention
The present invention relates to a plasma display panel (PDP) driving device and method.
2. Discussion of the Related Art
Generally, among flat panel displays, PDPs are regarded as having better luminance and light emission efficiency, as well as wider view angles. Therefore, PDPs are being considered as the primary substitute for the conventional cathode ray tubes for large displays of greater than 40 inches.
The PDP uses plasma generated via a gas discharge process to display characters or images, and tens of thousands to millions of pixels may be provided in a matrix, depending on its size. PDPs are categorized into direct current (DC) PDPs and alternating current (AC) PDPs according to supplied driving voltage waveforms and discharge cell structures.
Since the DC PDPs have electrodes exposed in the discharge space, they allow a current to flow when a voltage is supplied, which requires resistors for current restriction. On the other hand, since the AC PDPs have electrodes covered by a dielectric layer, naturally formed capacitances restrict the current, and the dielectric layer also protects the electrodes from ion shocks due to discharging. Accordingly, they have a longer lifespan than the DC PDP.
FIG. 1 shows a perspective view of a conventional AC PDP.
As shown, parallel pairs of a scan electrode 4 and a sustain electrode 5, covered by a dielectric layer 2 and a protection film 3, are provided on a lower surface of a first glass substrate 1. A plurality of address electrodes 8, covered with an insulation layer 7, is formed on an upper surface of a second glass substrate 6. Barrier ribs 9 are formed in parallel with, and between, the address electrodes 8, on the insulation layer 7, and phosphor layers 10 are formed on the surface of the insulation layer 7 and the sides of the barrier ribs 9. The first and second glass substrates 1 and 6 are sealed together to form a discharge space 11 between them, and the scan electrode 4 and the sustain electrode 5 pair are orthogonal to the address electrode 8. Discharge cells 12 are formed in the discharge space at intersections of the address electrode 8 and the scan electrode 4 and the sustain electrode 5 pair.
FIG. 2 shows a typical PDP electrode arrangement.
As shown, the PDP electrodes have an m×n matrix configuration. Address electrodes A1 to Am are arranged in the column direction, and scan electrodes Y1, to Yn (Y electrodes) and sustain electrodes X1 to Xn (X electrodes) are alternately arranged in the row direction.
FIG. 3 shows a conventional PDP driving waveform.
Each subfield includes a reset period, an address period, and a sustain period.
The reset period erases wall charge states of a previous sustain and sets up wall charges in order to stably perform a next addressing operation. In the address period, the cells that are to be turned on are selected, and wall charges are accumulated to those selected cells. In the sustain period, discharges for actually displaying images on the PDP are performed.
The following describes operations of the conventional reset period. As shown in FIG. 3, the conventional reset period may include an erase period, a Y ramp rising period, and a Y ramp falling period.
(1) Erase Period
Positive charges are accumulated on the X electrodes, and negative charges are accumulated on the Y electrodes after finishing the last sustain discharge. In this state, an erase ramp voltage that gently rises from 0 V to the voltage of +Ve is applied to the X electrode, thereby eliminating the wall charges formed on the X and Y electrodes.
(2) Y Ramp Rising Period
During this period, the address electrode and the X electrode maintain 0V, and a ramp voltage gradually rising from the voltage of Vs to the voltage of Vset is applied to the Y electrode. While the ramp voltage rises, a first weak reset discharge is generated to all the discharge cells from the Y electrode to the address electrode and the X electrode. As a result, negative wall charges accumulate to the Y electrode, and positive wall charges accumulate to the address electrode and the X electrode.
(3) Y Ramp Falling Period
In the latter part of the reset period, a ramp voltage that gradually falls from the voltage of Vs to the 0V is applied to the Y electrode while the X electrode maintains a voltage of Ve. While the ramp voltage falls, a second weak reset discharge is generated at all the discharge cells.
According to the conventional reset method shown in FIG. 3, a reset discharge is generated in the Y ramp rising period and the Y ramp falling period to control the amount of wall charges within the cell, and hence, an accurate addressing operation may be carried out subsequently.
In the Y falling ramp period, however, the discharge is not generated until the voltage at the Y electrode reaches a predetermined voltage. As shown in FIG. 3, during the Y ramp falling period, the voltage at the Y electrode falls to the voltage of Vs and maintains that voltage for a short period before gradually falling.
However, the voltage for actually generating the second discharge may be lower than the voltage of Vs. Hence, an unneeded period in which no discharge is generated may be provided after applying the Y ramp falling pulse, which increases the length of the reset period and the total driving time.